The present invention relates to data-processing systems that use non-volatile memory (NVM) for data and application storage, and methods for managing such storage. Systems and methods are disclosed for improving both the performance and durability of a data-processing system, such as an enhanced smartcard comprising both flash and Electrically-Erasable and -Programmable Read-Only Memories (EEPROM) NVM modules.
A typical example of such a data-processing system is a smartcard. Smartcards are plastic cards with embedded integrated circuits (ICs). Smartcards have been developed as an improvement to magnetic-stripe cards, and offer several advantages over magnetic-stripe cards. For example, the maximum storage capacity of a smartcard is much greater than that of a magnetic-stripe card. High-capacity SIM cards used for smartcard applications typically contain more than 256 KB of memory storage, many contain more than 64 MB memory storage Flash memory is a popular type of memory used in such applications.
Smartcards typically contain memory and a microcontroller (with associated logic memory and software). The data stored within a smartcard is accessed via an interface that is controlled by an operating system and security logic. An example of an advanced large-capacity smartcard is the MegaSIM™ card (available from msystems Ltd., Kefar Saba, Israel). MegaSIM™ cards enable smartcard vendors to provide storage capacity in the SIM (as opposed to external memory card storage) for a variety of advanced mobile services, such as downloading MMS (i.e. multimedia messaging services), MP3 (i.e. media player 3 standard), and video files, providing full personal information management (PIM) functionality, and enabling high-resolution image storage.
A High-capacity SIM card is a standard SIM card with extra storage memory. An EEPROM is part of the standard SIM functionality, and is used for keeping the SIM data files managed via an ISO-7816 SIM interface. Such data include encryption keys and SIM-based contact lists. The EEPROM is considered a highly-secure memory component because the EEPROM is part of the SIM controller, which is more secure than the storage memory. The storage memory is typically commercial flash memory with no special security mechanism. The storage memory is accessible through a high-speed interface (e.g. MMC, SD, and USB), and used to store user data such as pictures, music, video, and applications. Unlike the EEPROM, the storage memory is typically formatted as a standard FAT (File Allocation Table) file system, which is managed by the operating system of the host device (e.g. mobile phone), and not by the SIM card itself.
FIG. 1 is a simplified schematic block diagram of a prior-art data-processing system: a High-capacity SIM card 18. High-capacity SIM card 18 includes a SIM CPU 2 that is connected over a SIM bus 4 to several types of memory. A RAM 6 is a volatile memory mainly used for temporary data storage. RAM 6 is also used as application cache. A ROM 8 is permanent non-erasable storage used for storing the operating system and applications. Some systems might implement erasable memory storage instead of ROM 8 in order to provide flexibility in changing and enhancing the loaded software.
An EEPROM 10 is an electrically-erasable NVM that is byte-programmable. EEPROM 10 is mainly used for storing configuration-related information and, depending on the application, semi-permanent data as well. A large NAND-type flash memory 12 is also an electrically erasable NVM, but flash memory 12 is significantly larger in size than the EEPROM 10. Flash memory 12 is typically used for mass data storage, such as pictures, music, video, and databases (e.g. phone books). EEPROM 10 is erasable “word-by-word” in the sense that every time a word (i.e. the minimum number of bits that can be written to) is written to, the word is erased. Some EEPROMs also provide an optional block-erase command, which helps to write faster. This is in contrast to flash memory 12 that is erasable only “block-by-block.” Two interfaces are used for connecting the data-processing system with external devices (e.g. mobile phone). A high-speed interface 14A is used for accessing high-capacity storage and a low-speed interface 14B is an ISO 7816 interface for connection to legacy devices.
The components (SIM CPU 2, SIM bus 4, RAM 6, ROM 8, EEPROM 10, flash memory 12, and interfaces 14A and 14B) reside in a housing 16. Flash memory 12 includes user data 20, flash-memory management data 22, a FAT 24, and file-metadata directories 26. The logic that determines where to store each type of information (i.e. in user data 20 or management data 22) is handled by SIM CPU 2, which is responsible for managing the device resources.
High-capacity SIM card 18 resides in a mobile phone 28 with high-speed interface 14B operationally connected to a phone bus 30. Mobile phone 28 has a phone CPU 32 for performing phone operations, an I/O 34 that represents the user-interface components (e.g. keypad, microphone, speaker, and screen), and a memory 36 for storing an operating system 38 that manages the storage in flash memory 12.
Two major types of silicon-based, NVMs are relevant to the present invention:
(1) EEPROM devices are NVMs made of floating-gate transistors. EEPROM devices behave similarly to random-access memory (RAM); however, the write sequence of an EEPROM is slower than a RAM, and the number of writes to each location is limited to 100,000.
(2) Flash-memory devices are similar to EEPROM devices in that flash devices are also non-volatile, electrically-erasable and -programmable, read-only memories made of flash-type and floating-gate transistors. However, flash devices have certain limitations that make their use at the physical address level a bit sophisticated. In a flash device, it is not possible to rewrite a previously written area of the memory without a prior erase-operation of the area, meaning that the flash cells must be erased (e.g., programmed to “one-logic”) before they can be programmed again. EEPROM cells require such an erase-operation as well. The difference is that, in EEPROM, the erase-operation is performed internally by the device as part of the write-operation.
Flash devices are further divided into NAND-type flash devices and NOR-type flash devices. The major difference between NAND-type and NOR-type devices being that a NAND-type device is limited to block-read access, while a NOR-type device has random-read access. Erasure on a flash device can only be performed for relatively large groups of cells, usually called “erase blocks” which are typically 16-128 Kbytes in size in current commercial NAND-type devices (NOR-type devices have larger erase blocks). Therefore, updating the contents of a single byte, or a portion of a kilobyte, requires “housekeeping” operations (i.e. all sections of the erase block that are not to be updated must first be moved elsewhere so that they are preserved during erasure, and then those sections optionally are moved back into their original place).
Furthermore, NAND-type device blocks usually include some “bad blocks”. Such blocks are not reliable and their use should be avoided Blocks are designated as bad by the manufacturer during initial device testing, and later by application software when the blocks' failure is detected during use of the device in the field Flash devices, especially NAND-type devices, have higher densities, and are relatively inexpensive as compared to EEPROM devices. This makes a flash device very attractive as a solid-state hard-disk replacement.
To overcome limitations in flash devices of the prior art, a Flash File System (FFS) was disclosed in Ban, U.S. Pat. No. 5,404,485 (henceforth referred to as Ban '485), which is assigned to the assignee of the present invention, and is hereby incorporated by reference as if fully set forth herein. FFS provides a system of data storage and manipulation in flash devices that allows these devices to emulate magnetic disks. In the prior art, applications or operating systems interact with the flash storage sub-system using virtual addresses rather than physical addresses. There is an intermediary layer between the software application and the physical device that provides mapping from the virtual addresses to the physical addresses.
While the software may view the storage system as having a contiguous defect-free medium that can be read or written to randomly without limitations, the physical-addressing scheme has “holes” in the scheme's address range (due to bad blocks, for example), and portions of data that are adjacent to each other in the virtual address range might be separated in the physical address range. The intermediary layer that performs the mapping described above may be a software driver. Within a typical smartcard, the driver is run on the smartcard's embedded CPU. Alternatively, the intermediary layer may be embedded within a controller that controls the flash device, and serves as the interface for the main CPU of the host computer when the host computer accesses the storage.
Software or firmware implementations that perform such address mappings are typically called “flash management systems” or “flash file systems.” The latter term is a misnomer, as the implementations do not necessarily support “files” in the sense of files that are used in operating systems of personal computers, but rather support block device interfaces similar to those exported by hard-disk software drivers.
All types of silicon-based NVMs suffer from wear. This means that after a certain number of write/erase cycles, the probability that the relevant block or byte will malfunction is high. A typical number of data cycling (called data endurance) is 100,000 erase/write cycles, after which the probability that a location can no longer be erased is high.
Prior art devices using the above-described flash management system reserve a section of the flash memory for maintaining the management information (e.g. the mapping tables). Each time the flash device is updated with new data, the operation involves writing the actual data and another write of the updated management information. This process slows down the writing process as these two write-operations have to be performed serially. Another drawback of using the flash area for storing management information is due to the block-access nature of flash memory. The update of a single byte involves a full-page write-operation and possibly a block erase-operation, which makes this process even slower.
Another factor to be considered is the fact that a data-processing system typically organizes data in files that are associated with file metadata that typically contains the file name, size, attributes (e.g. access permissions), and the physical address of at least one sector that keeps the file data. The file metadata is kept in a directory and a FAT that records allocations of storage addresses to files. Prior art systems keep the FAT in a memory area assigned for this purpose within the same data-storage device. Writing a new file or updating an existing file involves several serial write-operations: one for writing the actual data, one for writing to the directory, and another one for writing to the FAT. If the storage device is a flash device, as described above, each of these write-operations actually involves two write-operations: one to write to the actual sector, and the other to update the flash management data. Although the management directory update may require writing only a few bytes, writing to a flash memory always requires a full-page write-operation and possibly a block erase-operation.
Prior art described in Chen, U.S. Pat. No. 6,456,528, suggests writing FAT data to a location within the same device that has two different methods of storing the information. This prior art discusses the benefit of storing the FAT using one method, and the data using the other. However, this prior art uses the same storage device for both data and management data. This prior art does not solve the problems of two serial write-operations, and the need for a full-page update as discussed in the present application.
Another example of a prior art system is described in Auclair and Harari, U.S. Pat. No. 5,778,418. This patent teaches a combination of a solid-state memory device and a rotating disk for enhancing the performance of the disk. The patent describes mapping between the logic-sector address and the physical data-storage location in either a mechanical hard drive or a solid-state memory device. This prior-art system does not address the problem of improving the efficiency of write-operations by differentiating between management-related data and the actual data to be written to the device as discussed in the present application.
It would be desirable to have a system that uses two independent storage devices. Such a system would allow the two write-operations described above (one for the user data and one for the management data) to be performed in parallel, thereby improving performance.